The subject system and method are generally directed to locating defects in chips and other complex electronic components. The system and method generally provide a process to diagnosis the location of the defects for multiple chips in one or more combined processes. In particular, although not exclusively, after incorrect outputs are detected in multiple chips with a common design, the system and method locate the cause of these incorrect outputs by diagnosing a single simulated chip bearing the collective incorrect outputs of the multiple chips, and then distributing this diagnosis among the individual chips.
Integrated circuits (“chips”), circuit boards, printed electronics, and other complex electronic circuits and devices are presently manufactured on a mass scale. (Hereinafter this description will refer to “chips” for convenience, but the principles described herein are also applicable to other circuit implementations unless otherwise specified.) While the processes involved in the manufacture may vary, none are flawless. Therefore, manufacturing testing of the chips is necessary to determine whether defects have arisen.
Because of the small size of circuit lines in modern circuitry, frequently on the nanometer scale, direct examination is not practical. Rather, initial manufacturing testing generally involves providing a chip with a series of inputs, and confirming that the chip produces the proper output in response.
If a fault in a chip is detected, a manufacturer may simply stop and discard the chip. However, this approach is wasteful, and may leave a reparable flaw in the manufacturing process itself undetected, leaving the following manufacturing run vulnerable to the same defects.
Therefore, a manufacturer may instead further diagnose the chip to determine the location of the defect. This may assist in repair of the defect, and in avoidance of similar defects in later manufacturing runs. By evaluating which outputs of a chip have failed and tracing the course of the failures back through the various circuit paths of the chip, then conducting further simulation as necessary, the defect which causes the failure may be located.
However, a complex chip may contain thousands or even millions of paths and points of potential defect, and therefore the complexity of the problem requires considerable time and simulation resources to resolve for each chip. As a manufacturing run may have hundreds or thousands of chips, simulating for each defective chip can be enormously time-consuming. Therefore, although chips may be manufactured in a rapid manner, the testing of these chips creates a bottleneck in the ability of a manufacturer to confirm whether they are ready for the consumer.
There is therefore a need for a more efficient testing procedure, which may determine the location of a defect in one or more chips more quickly.